firmware.elf: file format elf32-msp430 Disassembly of section .text: 0000c000 <__watchdog_support>: c000: 55 42 20 01 mov.b &0x0120,r5 c004: 35 d0 08 5a bis #23048, r5 ;#0x5a08 c008: 82 45 02 02 mov r5, &0x0202 0000c00c <__init_stack>: c00c: 31 40 00 04 mov #1024, r1 ;#0x0400 0000c010 <__do_copy_data>: c010: 3f 40 00 00 mov #0, r15 ;#0x0000 c014: 0f 93 tst r15 c016: 08 24 jz $+18 ;abs 0xc028 c018: 92 42 02 02 mov &0x0202,&0x0120 c01c: 20 01 c01e: 2f 83 decd r15 c020: 9f 4f d6 c1 mov -15914(r15),512(r15);0xc1d6(r15), 0x0200(r15) c024: 00 02 c026: f8 23 jnz $-14 ;abs 0xc018 0000c028 <__do_clear_bss>: c028: 3f 40 02 00 mov #2, r15 ;#0x0002 c02c: 0f 93 tst r15 c02e: 07 24 jz $+16 ;abs 0xc03e c030: 92 42 02 02 mov &0x0202,&0x0120 c034: 20 01 c036: 1f 83 dec r15 c038: cf 43 00 02 mov.b #0, 512(r15);r3 As==00, 0x0200(r15) c03c: f9 23 jnz $-12 ;abs 0xc030 0000c03e
: /** * Main routine */ int main(void) { c03e: 21 82 sub #4, r1 ;r2 As==10 WDTCTL = WDTPW + WDTHOLD; // Stop WDT c040: b2 40 80 5a mov #23168, &0x0120 ;#0x5a80 c044: 20 01 BCSCTL1 = CALBC1_1MHZ; // Set DCO c046: d2 42 ff 10 mov.b &0x10ff,&0x0057 c04a: 57 00 DCOCTL = CALDCO_1MHZ; c04c: d2 42 fe 10 mov.b &0x10fe,&0x0056 c050: 56 00 P1DIR = BIT0 + BIT6; // P1.0 and P1.6 are the red+green LEDs c052: f2 40 41 00 mov.b #65, &0x0022 ;#0x0041 c056: 22 00 P1OUT = BIT0 + BIT6; // All LEDs off c058: f2 40 41 00 mov.b #65, &0x0021 ;#0x0041 c05c: 21 00 uart_init(); c05e: b0 12 e2 c0 call #0xc0e2 // register ISR called when data was received uart_set_rx_isr_ptr(uart_rx_isr); c062: 3f 40 d8 c0 mov #-16168,r15 ;#0xc0d8 c066: b0 12 12 c1 call #0xc112 __bis_SR_register(GIE); c06a: 32 d2 eint uart_puts((char *)"\n\r***************\n\r"); c06c: 3f 40 6c c1 mov #-16020,r15 ;#0xc16c c070: b0 12 34 c1 call #0xc134 uart_puts((char *)"MSP430 harduart\n\r"); c074: 3f 40 80 c1 mov #-16000,r15 ;#0xc180 c078: b0 12 34 c1 call #0xc134 uart_puts((char *)"***************\n\r\n\r"); c07c: 3f 40 92 c1 mov #-15982,r15 ;#0xc192 c080: b0 12 34 c1 call #0xc134 uart_puts((char *)"PRESS any key to start echo example ... "); c084: 3f 40 a6 c1 mov #-15962,r15 ;#0xc1a6 c088: b0 12 34 c1 call #0xc134 unsigned char c = uart_getc(); c08c: b0 12 18 c1 call #0xc118 uart_putc(c); c090: b0 12 26 c1 call #0xc126 uart_puts((char *)"\n\rOK\n\r"); c094: 3f 40 cf c1 mov #-15921,r15 ;#0xc1cf c098: b0 12 34 c1 call #0xc134 volatile unsigned long i; while(1) { P1OUT ^= BIT6; // Toggle P1.6 output (green LED) using exclusive-OR c09c: f2 e0 40 00 xor.b #64, &0x0021 ;#0x0040 c0a0: 21 00 i = 50000; // Delay c0a2: b1 40 50 c3 mov #-15536,0(r1) ;#0xc350, 0x0000(r1) c0a6: 00 00 c0a8: 81 43 02 00 mov #0, 2(r1) ;r3 As==00, 0x0002(r1) do (i--); // busy waiting (bad) c0ac: 2e 41 mov @r1, r14 c0ae: 1f 41 02 00 mov 2(r1), r15 ;0x0002(r1) c0b2: 3e 53 add #-1, r14 ;r3 As==11 c0b4: 3f 63 addc #-1, r15 ;r3 As==11 c0b6: 81 4e 00 00 mov r14, 0(r1) ;0x0000(r1) c0ba: 81 4f 02 00 mov r15, 2(r1) ;0x0002(r1) while (i != 0); c0be: 2e 41 mov @r1, r14 c0c0: 1f 41 02 00 mov 2(r1), r15 ;0x0002(r1) c0c4: 0e 93 tst r14 c0c6: f2 23 jnz $-26 ;abs 0xc0ac c0c8: 0f 93 tst r15 c0ca: f0 23 jnz $-30 ;abs 0xc0ac c0cc: e7 3f jmp $-48 ;abs 0xc09c 0000c0ce <__stop_progExec__>: c0ce: 32 d0 f0 00 bis #240, r2 ;#0x00f0 c0d2: fd 3f jmp $-4 ;abs 0xc0ce 0000c0d4 <__ctors_end>: c0d4: 30 40 6a c1 br #0xc16a 0000c0d8 : #include #include "uart.h" void uart_rx_isr(unsigned char c) { uart_putc(c); c0d8: b0 12 26 c1 call #0xc126 P1OUT ^= BIT0; // toggle P1.0 (red led) c0dc: d2 e3 21 00 xor.b #1, &0x0021 ;r3 As==01 } c0e0: 30 41 ret 0000c0e2 : IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt } void uart_set_rx_isr_ptr(void (*isr_ptr)(unsigned char c)) { uart_rx_isr_ptr = isr_ptr; c0e2: 82 43 00 02 mov #0, &0x0200 ;r3 As==00 void uart_init(void) { uart_set_rx_isr_ptr(0L); P1SEL = RXD + TXD; c0e6: f2 40 06 00 mov.b #6, &0x0026 ;#0x0006 c0ea: 26 00 P1SEL2 = RXD + TXD; c0ec: f2 40 06 00 mov.b #6, &0x0041 ;#0x0006 c0f0: 41 00 UCA0CTL1 |= UCSSEL_2; // SMCLK c0f2: f2 d0 80 ff bis.b #-128, &0x0061 ;#0xff80 c0f6: 61 00 UCA0BR0 = 104; // 1MHz 9600 c0f8: f2 40 68 00 mov.b #104, &0x0062 ;#0x0068 c0fc: 62 00 UCA0BR1 = 0; // 1MHz 9600 c0fe: c2 43 63 00 mov.b #0, &0x0063 ;r3 As==00 UCA0MCTL = UCBRS0; // Modulation UCBRSx = 1 c102: e2 43 64 00 mov.b #2, &0x0064 ;r3 As==10 UCA0CTL1 &= ~UCSWRST; // Initialize USCI state machine c106: f2 f0 fe ff and.b #-2, &0x0061 ;#0xfffe c10a: 61 00 IE2 |= UCA0RXIE; // Enable USCI_A0 RX interrupt c10c: d2 d3 01 00 bis.b #1, &0x0001 ;r3 As==01 } c110: 30 41 ret 0000c112 : void uart_set_rx_isr_ptr(void (*isr_ptr)(unsigned char c)) { uart_rx_isr_ptr = isr_ptr; c112: 82 4f 00 02 mov r15, &0x0200 } c116: 30 41 ret 0000c118 : unsigned char uart_getc() { while (!(IFG2&UCA0RXIFG)); // USCI_A0 RX buffer ready? c118: 5f 42 03 00 mov.b &0x0003,r15 c11c: 1f f3 and #1, r15 ;r3 As==01 c11e: fc 27 jz $-6 ;abs 0xc118 return UCA0RXBUF; c120: 5f 42 66 00 mov.b &0x0066,r15 } c124: 30 41 ret 0000c126 : void uart_putc(unsigned char c) { while (!(IFG2&UCA0TXIFG)); // USCI_A0 TX buffer ready? c126: 5e 42 03 00 mov.b &0x0003,r14 c12a: 2e f3 and #2, r14 ;r3 As==10 c12c: fc 27 jz $-6 ;abs 0xc126 UCA0TXBUF = c; // TX c12e: c2 4f 67 00 mov.b r15, &0x0067 } c132: 30 41 ret 0000c134 : void uart_puts(const char *str) { c134: 0b 12 push r11 c136: 0b 4f mov r15, r11 while(*str) uart_putc(*str++); c138: 03 3c jmp $+8 ;abs 0xc140 c13a: 1b 53 inc r11 c13c: b0 12 26 c1 call #0xc126 c140: 6f 4b mov.b @r11, r15 c142: 4f 93 tst.b r15 c144: fa 23 jnz $-10 ;abs 0xc13a } c146: 3b 41 pop r11 c148: 30 41 ret 0000c14a : interrupt(USCIAB0RX_VECTOR) USCI0RX_ISR(void) { c14a: 0f 12 push r15 c14c: 0e 12 push r14 c14e: 0d 12 push r13 c150: 0c 12 push r12 if(uart_rx_isr_ptr != 0L) { c152: 1e 42 00 02 mov &0x0200,r14 c156: 0e 93 tst r14 c158: 03 24 jz $+8 ;abs 0xc160 (uart_rx_isr_ptr)(UCA0RXBUF); c15a: 5f 42 66 00 mov.b &0x0066,r15 c15e: 8e 12 call r14 } } c160: 3c 41 pop r12 c162: 3d 41 pop r13 c164: 3e 41 pop r14 c166: 3f 41 pop r15 c168: 00 13 reti 0000c16a <_unexpected_>: c16a: 00 13 reti Disassembly of section .vectors: 0000ffe0 <__ivtbl_16>: ffe0: d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 4a c1 ..............J. fff0: d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 d4 c0 00 c0 ................